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Verilog Gate level Modeling examples

Following examples will help you a clear out understanding of Gate Level Modelling of Verilog. Example-1: Simulate four input OR gate Verilog code: module orgate(out, a, b, c, d); input a, b, c, d; wire x, y; output out; or or1(x, a, b); or or2(y, c, d); or orfinal(out, x, y); endmodule In the above Verilog code, we have used wire concept. Wires are used to connect modules just like on the breadboard. An output of one module is an input to another module and this can be performed by using wire. Wire ‘x’ and wire ‘y’ is the input to...

Introduction to Modelsim Tutorial

Modelsim is a simulator and is used to simulate HDL languages including Verilog, VHDL etc. Modelsim is a product of Mentor Graphics and can be easily downloaded with student edition from here: Download Modelsim with Student Licence This tutorial will explain on how to use Modelsim and how you can use it to program modules in Verilog. See this article “Introduction to Verilog“ if you don’t know Verilog at all. As explained in “Introduction to Verilog” we will implement “andgate” module in Modelsim Open Modelsim after installing it. Goto File->New->Project and click Project. After selecting Project a new window will...

Introduction to Verilog

This is an introductory article on how to program digital electronics in Verilog and simulate the result in Modelsim. Verilog is a hardware language it is different from conventional High level language like C/C++. You need to think in a hardware style like how hardware works ? how these digital gates work ? This tutorial will help you in understanding basics of Verilog and will present some examples on how you can simulate your digital circuit on Modelsim using Verilog. See Tutorial on Modelsim here Introduction: Verilog is Hardware descriptive language (HDL) and is standardized as IEEE 1364. The code...

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