Design of 4×2 Multiplexer using 2×1 mux in Verilog

In our previous article “Hierarchical Design of Verilog” we have mentioned few examples and explained how one can design Full Adder using two Half adders. This example problem will focus on how you can construct 4×2 multiplexer using 2×1 multiplexer in Verilog. A multiplexer is a device that can transmit several digital signals on one line by selecting certain switches. For example, in a 2×1 multiplexer, there is one select switch and two data lines. You can select a data line by setting a switch to 0 or 1 as shown in the diagram below: From above figure, we...

Verilog Gate level Modeling examples

Following examples will help you a clear out understanding of Gate Level Modelling of Verilog. Example-1: Simulate four input OR gate Verilog code: module orgate(out, a, b, c, d); input a, b, c, d; wire x, y; output out; or or1(x, a, b); or or2(y, c, d); or orfinal(out, x, y); endmodule In the above Verilog code, we have used wire concept. Wires are used to connect modules just like on the¬†breadboard. An¬†output of one module is an input to another module and this can be performed by using wire. Wire ‘x’ and wire ‘y’ is the input to...