Half Adder and Full Adder using Hierarchical Designing in Verilog

This tutorial focuses on writing Verilog code in hierarchical style. In “Introduction to Verilog” we have mentioned that it is a good practice to write modules for each block. This tutorial will further provide some examples and explain why it is better to code in hierarchical style. Hierarchical Designing: A Hierarchical methodology is used to design simple components to construct more complex component. The key idea is to divide and conquer i.e. to divide the big complex circuit into smaller modules and further dividing these modules to even smaller modules like gates etc. There are two design approaches when writing a code...