Introduction to Modelsim Tutorial

Modelsim is a simulator and is used to simulate HDL languages including Verilog, VHDL etc. Modelsim is a product of Mentor Graphics and can be easily downloaded with student edition from here: Download Modelsim with Student Licence This tutorial will explain on how to use Modelsim and how you can use it to program modules in Verilog. See this article “Introduction to Verilog“ if you don’t know Verilog at all. As explained in “Introduction to Verilog”¬†we will implement “andgate” module in Modelsim Open Modelsim after installing it. Goto File->New->Project and click Project. After selecting Project a new window will...