Half Adder and Full Adder using Hierarchical Designing in Verilog

This tutorial focuses on writing Verilog code in hierarchical style. In “Introduction to Verilog” we have mentioned that it is a good practice to write modules for each block. This tutorial will further provide some examples and explain why it is better to code in hierarchical style. Hierarchical Designing: A Hierarchical methodology is used to design simple components to construct more complex component. The key idea is to divide and conquer i.e. to divide the big complex circuit into smaller modules and further dividing these modules to even smaller modules like gates etc. There are two design approaches when writing a code...

Verilog Gate level Modeling examples

Following examples will help you a clear out understanding of Gate Level Modelling of Verilog. Example-1: Simulate four input OR gate Verilog code: module orgate(out, a, b, c, d); input a, b, c, d; wire x, y; output out; or or1(x, a, b); or or2(y, c, d); or orfinal(out, x, y); endmodule In the above Verilog code, we have used wire concept. Wires are used to connect modules just like on the breadboard. An output of one module is an input to another module and this can be performed by using wire. Wire ‘x’ and wire ‘y’ is the input to...

Introduction to Modelsim Tutorial

Modelsim is a simulator and is used to simulate HDL languages including Verilog, VHDL etc. Modelsim is a product of Mentor Graphics and can be easily downloaded with student edition from here: Download Modelsim with Student Licence This tutorial will explain on how to use Modelsim and how you can use it to program modules in Verilog. See this article “Introduction to Verilog“ if you don’t know Verilog at all. As explained in “Introduction to Verilog” we will implement “andgate” module in Modelsim Open Modelsim after installing it. Goto File->New->Project and click Project. After selecting Project a new window will...