Verilog Simulation and FPGA setup using Xilinx Project Navigator

In this tutorial, we will walk you through the steps on how you can simulate a Verilog program in Xilinx Project Navigator. For this tutorial, we have Xilinx ISE 14.4. Make sure you have installed Xilinx ISE 14.4 or later. Follow the below-mentioned procedure to simulate your first Verilog program. Open 32/64-bit Project Navigator. Click “OK” to close the ‘Tip of the Day’ window that pops up. You can uncheck “Show Tips at Startup” if you do not want the “Tip of the Day” to popup every time you start the tool. Now create a new project by clicking...

Data-flow Modeling, Operators and their Precendence in Verilog

In this tutorial, you will learn data-flow modeling style of Verilog HDL (Hardware Descriptive Language) Objectives you will achieve after this tutorial: Define expressions, operators, and operands. Explain assignment delay, implicit assignment delay, and net declaration delay for continuous assignment statements Describe the continuous assignment (“assign”) statement, restrictions on the assign statement, and the implicit continuous assignment statement. List operator types for all possible operations-arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, and conditional and their precendence Introduction: The gate-level modeling approach is suitable for smaller circuits and it’s more intuitive to a designer with basic knowledge of digital...

Design of 4×2 Multiplexer using 2×1 mux in Verilog

In our previous article “Hierarchical Design of Verilog” we have mentioned few examples and explained how one can design Full Adder using two Half adders. This example problem will focus on how you can construct 4×2 multiplexer using 2×1 multiplexer in Verilog. A multiplexer is a device that can transmit several digital signals on one line by selecting certain switches. For example, in a 2×1 multiplexer, there is one select switch and two data lines. You can select a data line by setting a switch to 0 or 1 as shown in the diagram below: From above figure, we...