Posted on Jan 20, 2017
Following examples will help you a clear out understanding of Gate Level Modelling of Verilog. Example-1: Simulate four input OR gate Verilog code: module orgate(out, a, b, c, d); input a, b, c, d; wire x, y; output out; or or1(x, a, b); or or2(y, c, d); or orfinal(out, x, y); endmodule In the above Verilog code, we have used wire concept. Wires are used to connect modules just like on the breadboard. An output of one module is an input to another module and this can be performed by using wire. Wire ‘x’ and wire ‘y’ is the input to...