In this tutorial, you will learn the data-flow modeling style of Verilog HDL (Hardware Descriptive Language)

Objectives you will achieve after this tutorial:

• Define expressions, operators, and operands.
• Explain assignment delay, implicit assignment delay, and net declaration delay for continuous assignment statements
• Describe the continuous assignment (“assign”) statement, restrictions on the assign statement, and the implicit continuous assignment statement.
• List operator types for all possible operations-arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, and conditional and their precendence

Introduction:

The gate-level modeling approach is suitable for smaller circuits and it’s more intuitive to a designer with basic knowledge of digital logic design. However, in complex design, designing in gate-level modeling is a challenging and highly complex task and that’s where data-flow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than the instantiation of individual gates.

Continuous Assignment:

A continuous assignment is used to drive a value onto a net. A continuous assignment statement starts with the keyword assign. The keyword assign declares a continuous assignment that binds the Boolean expression on the right-hand side (RHS) of the statement to the variable on the left-hand side (LHS). Verilog arithmetic and logical operations can be used in assign expressions along with delays as well. The syntax of assign is as follows:

assign <delay> <net_name> = <expression>;
assign #10 out = in1 & in2; //delay is used

Implicit Continuous Assignment: Instead of declaring a net and then writing a continuous assignment on the net, Verilog provides a shortcut by which a continuous assignment can be placed on a net when it is declared

//Regular continuous assignment
wire out;
assign out = in1 & in2;

//Same effect is achieved by an implicit continuous assignment
wire out = in1 & in2;

Using operators is the main part of data flow modeling. Most of them are similar to C-Programming language and have the same uses as in other programming languages. Learning how to use these operators is an important objective of dataflow modeling. Some of these operators and their precedence is given below:

OPERATORS AND OPERATOR TYPES

Verilog provides different types of operators which act as operands. Some of the operators are described below:

 Verilog Operator Name Functional Group [ ] bit-select or part-select ( ) parenthesis ! ~ & | ~& ~| ^ ~^ or ^~ logical negation negation reduction AND reduction OR reduction NAND reduction NOR reduction XOR reduction XNOR logical bit-wise reduction reduction reduction reduction reduction reduction + – unary (sign) plus unary (sign) minus arithmetic arithmetic { } concatenation concatenation {{ }} replication replication * / % multiply divide modulus arithmetic arithmetic arithmetic + – binary plus binary minus arithmetic arithmetic << >> shift left shift right shift shift > >= < <= greater than greater than or equal to less than less than or equal to relational relational relational relational == != case equality case inequality equality equality & ^ | bit-wise AND bit-wise XOR bit-wise OR bit-wise bit-wise bit-wise && || logical AND logical OR logical logical ?: conditional conditional

I recommend going through basic practice with these operators on Modelsim or Xilinx. As these things can only be learned by practicing.

Operator Precedence:
Operator Precedence is given below:

 Verilog Operator Operator Symbol Precedence Unary, Multiply, Divide, Modulus + – ! ~ * / % High Precendence Add, Subtract, Shift + – << >> Relational Equality < <= > >= == != !== Reduction Logical &  ~& ^  ^~ |  ~| && || Conditional ?: Lowest Precedence

Examples related to above-mentioned operators and dataflow modeling is provided Here.